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EM78P447S
I.
GENERAL DESCRIPTION
EM78P447S is an 8-bit microprocessor with low-power and high-speed CMOS technology. There is a 4096*13bit Electrical One Time Programmable Read Only Memory (OTP-ROM) within it. It provides a PROTECTION bit to prevent a user's code from intruding as well as 8 other OPTION bits to match the user's requirements. Because of the OTP-ROM, the EM78P447S offers users a convenient way to develop and verify their programs. Moreover, a user's developed code can be programmed easily by an EMC writer.
II.
FEATURES
* * * * Operating voltage range: 2.2V~5.5V Available in temperature range: 0C~70C Operating frequency range: DC ~ 20MHz Low power consumption: * less than 2.2 mA at 5V/4MHz * typical of 30A at 3V/32KHz * typical of 1A during the sleep mode 4096 x 13 bits on chip ROM 148 x 8 bits on chip registers (SRAM) 3 bi-directional I/O ports 5 level stacks for subroutine and interrupt 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Power-down mode (SLEEP mode) Two available interruptions * TCC overflow interrupt * External interrupt(INT pin) Programmable free running watchdog timer 10 programmable pull-high I/O pins 2 programmable R-option I/O pins 2 programmable open-drain I/O pins Two clocks per instruction cycle 99.9% single instruction cycle commands Package type: * 28 pin DIP and SOIC (EM78P447SA) * 32 pin DIP and SOIC (EM78P447SB)
* * * * * * *
* * * * * * *
* This specification is subject to be changed without notice.
B3-1
12.29.1999
EM78P447S
III. PIN ASSIGNMENTS
EM78P447SA
TCC VDD NC VSS /INT P50 P51 P52 P53 P60 P61 P62 P63 P64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 /RESET OSCI OSCO P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65
EM78P447SB
P55 P54 TCC VDD NC VSS /INT P50 P51 P52 P53 P60 P61 P62 P63 P64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P56 P57 /RESET OSCI OSCO P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65
DIP, SOIC
DIP, SOIC
Fig. 1 Pin assignments
IV. FUNCTIONAL BLOCK DIAGRAM
OSCI
OSCO
/RESET TCC /INT
Oscillator/Timing Control
WDT Timer
PC
Prescaler
Stack Stack Stack Stack Stack
ROM
WDT Time-out
IOCA
R1(TCC)
Interrupt Controller
Instruction register
ALU
RAM
Instruction Decoder R4
Sleep & Wake Control
R3
ACC
DATA & CONTROL BUS
IOC5 R5
IOC6 R6
IOC7 R7
PPPPPPPP 55555555 01234567
PPPPPPPP 66666666 01234567
PPPPPPPP 77777777 01234567
Fig. 2 Functional block diagram
* This specification is subject to be changed without notice.
B3-2
12.29.1999
EM78P447S
V. PIN DESCRIPTION
* * * * * * * * * * * * * * Function Power supply. XTAL type : Crystal input terminal or external clock input pin. RC type : RC oscillator input pin. XTAL type : Output terminal for crystal oscillator or external clock input pin. RC type : Instruction clock out. External clock signal input. External interrupt pin triggered by falling edge. General-purpose I/O pin. General-purpose I/O pin. General-purpose I/O pin. If the pin remains logic low, the device will be in reset. No connection. External Counter input. Ground.
Table 1 Pin description -EM78P447SA Symbol Type VDD OSCI I OSCO I/O
/INT P70~P77 P60~P67 P50~P53 /RESET NC TCC VSS
I I/O I/O I/O I I -
Table 2 Pin description -EM78P447SB Symbol Type VDD OSCI I OSCO I/O
* * * * * * * * * * * * * *
/INT P70~P77 P60~P67 P50~P57 /RESET NC TCC VSS
I I/O I/O I/O I I -
Function Power supply. XTAL type : Crystal input terminal or external clock input pin. RC type : RC oscillator input pin. XTAL type : Output terminal for crystal oscillator or external clock input pin. RC type : Instruction clock out. External clock signal input. External interrupt pin triggered by falling edge. General-purpose I/O pin. General-purpose I/O pin. General-purpose I/O pin. If the pin remains logic low, the device will be in reset. No connection. External Counter input. Ground.
* This specification is subject to be changed without notice.
B3-3
12.29.1999
EM78P447S
VI. FUNCTION DESCRIPTIONS
VI.1 Operational Registers 1. R0 (Indirect Addressing Register) R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses the data pointed by the RAM Select Register (R4). 2. R1 (Time Clock /Counter) * Increased by an external signal edge which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. * The signals to increase the counter are decided by bit 4 and bit 5 of the CONT register. * Writable and readable as any other registers. 3. R2 (Program Counter) & Stack * Depending on the device type, R2 and hardware stacks are 12-bit wide. The structure is depicted in Fig. 3. * Generating 4096x13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. * The contents of R2 are set all "0"s upon a RESET condition. * "JMP" instruction allows the direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. * "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can locate anywhere within a page. * "RET" ("RETL K", "RETI") instruction loads the program counter with the contents of the top-level stack. * "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and tenth bits of the PC are cleared. * "MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared. * Any instruction which would modify the contents of R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2, 6",......) will cause the ninth bit and the tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page. * The two most significant bits (A11 and A10) will be loaded with the contents of PS1 and PS0 in the status register (R3) upon the execution of a "JMP", "CALL", or any other instructions which would change the contents of R2. * All instructions are single instruction cycle (fclk/2) except the instructions which would change the contents of R2 need one more instruction cycle.
* This specification is subject to be changed without notice.
B3-4
12.29.1999
EM78P447S
CALL
PC
A11 A10
A9 A8
A7 ~ A0
RET RETI RETL
Stack 1 Stack 2 Stack 3 Stack 4 Stack 5
000
00
Page 0
3FF 400
001: Hareware interrupt location 002: Software interrupt (INT instruction) location FFF: Reset location
01
Page 1
7FF 800
10
Page 2
BFF C00
11
Page 3
FFF
Fig. 3 Program counter organization 4. R3 (Status Register) 7 GP * * * * * * 6 PS1 5 PS0 4 T 3 P 2 Z 1 DC 0 C
Bit 0 (C) Bit 1 (DC) Bit 2 (Z) Bit 3 (P)
Carry flag Auxiliary carry flag Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Power-down bit. Set to 1 during power-on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T) Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands, or during power-up and reset to 0 by WDT time-out. Bit 5 (PS0) ~ 6 (PS1) Page-selecting bits. PS0~PS1 are used to select a program memory page. When executing "JMP", "CALL", or other instructions which cause the program counter to be changed (e.g. MOV R2,A), PS0~PS1 are loaded to the 11th and 12th bits of the program counter which would select one of the available program memory pages. Note that RET, RETL and RETI instructions do not change the PS0~PS1 bits. That is, the return will be always to the page from the place where the subroutine was called, regardless of the current setting of PS0~PS1 bits.
* This specification is subject to be changed without notice.
B3-5
12.29.1999
EM78P447S
PS1 0 0 1 1 * 5. Bit 7(GP)
PS0 0 1 0 1 General read/write bit.
Program memory page [Address] Page 0 [000-3FF] Page 1 [400-7FF] Page 2 [800-BFF] Page 3 [C00-FFF]
R4 (RAM Select Register) * * * Bits 0~5 are used to select registers (address: 00~3F) in the indirect addressing mode. Bit 6~7 are used to select bank 0 ~ 4. See the configuration of the data memory in Fig. 4.
6.
R5 ~ R7 (Port 5 ~ Port 7) * R5, R6 and R7 are I/O registers.
7.
R8~R1F, R20~R3E(General-purpose Register) * R8~R1F and R20~R3E (including Bank 0~3) are general-purpose registers.
8. R3F (Interrupt Status Register) 7 * * * * * * * 6 5 4 3 EXIF 2 1 0 TCIF
Bit 0 (TCIF) TCC overflowing interrupt flag. Set when TCC overflows, reset by software. Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software. Bits1~2 and 4~7 Not used. "1" means interrupt request, and "0" means non-interrupt occurrence. R3F can be cleared by instruction but can not be set. IOCF is the interrupt control register. Note that the result of reading R3F is the "logic AND" of R3F and IOCF.
* This specification is subject to be changed without notice.
B3-6
12.29.1999
EM78P447S
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
R0 R1(TCC) R2(PC) R3(Status) R4(RSR) R5(Port5) R6(Port6) R7(Port7) R8 R9 RA RB RC RD RE RF
Stack (5 levels) IOC5 IOC6 IOC7
IOCE IOCF
10 : : 1F
16x8 Common Register
20 : :
00 31x8 Bank Register (Bank 0)
01 31x8 Bank Register (Bank 1)
10 31x8 Bank Register (Bank 2)
11 31x8 Bank Register (Bank 3)
3E 3F
R3F
Fig. 4 Data memory configuration VI.2 Special Purpose Registers 1. A (Accumulator) * Internal data transfer, or instruction operand holding * It can not be addressed. 2. CONT (Control Register) 7 /PHEN 6 /INT 5 TS 4 TE 3 PAB 2 PSR2 1 PSR1 0 PSR0
* Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
* This specification is subject to be changed without notice.
B3-7
12.29.1999
EM78P447S
PSR2 0 0 0 0 1 1 1 1
PSR1 0 0 1 1 0 0 1 1
PSR0 0 1 0 1 0 1 0 1
TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
* Bit 3 (PAB) Prescaler assignment bit. 0: TCC. 1: WDT. * Bit 4 (TE) TCC signal edge 0: increment if the transition from low to high takes place on the TCC pin. 1: increment if the transition from high to low takes place on the TCC pin. * Bit 5 (TS) TCC signal source 0: internal instruction cycle clock. 1: transition on the TCC pin. * Bit 6 (INT) Interrupt enable flag 0: masked by DISI or hardware interrupt. 1: enabled by the ENI/RETI instruction. * Bit 7 (/PHEN) Control bit used to enable the pull-high of the P60~P67, P74 and P75 pins. 0: Enable internal pull-high. 1: Disable internal pull-high. * CONT register is both readable and writable. 3. IOCB (Wake-up Control Register for Port6) 7 /WUE7 6 /WUE6 5 /WUE5 4 /WUE4 3 /WUE3 2 /WUE2 1 /WUE1 0 /WUE0
* Bit 0 (/WUE0) Control bit used to enable the wake-up function of P60 pin. 0: Enable the wake-up function. 1: Disable the wake-up function. * Bit 1 (/WUE1) Control bit used to enable the wake-up function of P61 pin. * Bit 2 (/WUE2) Control bit used to enable the wake-up function of P62 pin. * Bit 3 (/WUE3) Control bit used to enable the wake-up function of P63 pin. * Bit 4 (/WUE4) Control bit used to enable the wake-up function of P64 pin. * Bit 5 (/WUE5) Control bit used to enable the wake-up function of P65 pin. * Bit 6 (/WUE6) Control bit used to enable the wake-up function of P66 pin. * Bit 7 (/WUE7) Control bit used to enable the wake-up function of P67 pin.
* This specification is subject to be changed without notice.
B3-8
12.29.1999
EM78P447S
4. IOCE (WDT Control Register) 7 6 ODE 5 WTE 4 SLPC 3 ROC 2 1 0 /WUE
* Bit 0 (/WUE) Control bit used to enable the wake-up function of P74 and P75. 0: Enable the wake-up function. 1: Disable the wake-up function. * Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins (P70, P71) to be read by the controller. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P71 pin or/and P70 pin to VSS by a 560K external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P70 (P71) will be read as "0"/"1". Refer to Fig. 7(b). * Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared in software. SLPC is used to control the operation of oscillator. The oscillator is disabled (oscillator is stopped, and the controller enters the SLEEP2 mode) on the high-to-low transition and is enabled (the controller is awakened from SLEEP2 mode) on the low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18 ms (oscillator start-up timer, OST) before the next instruction of program being executed. The OST is always activated by wake-up from sleep mode whether the Code option bit WTC is "0" or not. After waking up, the WDT is enabled if Code Option WTC is "1". The block diagram of SLEEP2 mode and wake-up caused by input triggered are depicted in Fig. 5. * Bit 5 (WTE) Control bit used to enable Watchdog Timer. The WTE bit is used only if WTC, the CODE option bit, is "1". If the WTC bit is "1", then WDT can be disabled/ enabled by the WTE bit. 0: Disable WDT. 1: Enable WDT. The WTE bit is not used if WTC, the CODE option bit WTC, is "0". That is, if the WTC bit is "0", WDT is always disabled no matter what the WTE bit is. * Bit 6 (ODE) Control bit used to enable the open-drain of P76 and P77 pins. 0: Disable open-drain output 1: Enable open-drain output * IOCE register is both readable and writable. * Bits 1~2,7 Not used. 5. IOCF (Interrupt Mask Register) 7 6 5 4 3 EXIE 2 1 0 TCIE
* Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt * Bit 2 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt * Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
* This specification is subject to be changed without notice.
B3-9
12.29.1999
EM78P447S
* * Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 9. IOCF register is both readable and writable.
WUE0
Oscillator
Enable Disable WUE1
Reset 1
Q P R C L D
VCC
CLK Q
8 Clear From S/W Set
WUE7
P60~P67 VCC
WUE PHEN 2 P74~P75
Fig. 5 VI.3 TCC/WDT & Prescaler
Block diagram of sleep mode and wake-up circuits on I/O ports
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available only for either the TCC or the WDT at the same time and the PAB bit of the CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler will be cleared by the instructions which write to TCC each time, when assigned to TCC mode. The WDT and prescaler, when assigned to WDT mode, will be cleared by the WDTC" and "SLEP" instructions. Fig. 6 depicts the circuit diagram of TCC/WDT. * R1(TCC) is an 8-bit timer/counter. The clock source of TCC can be internal clock or external clock input (edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 in every instruction cycle (without prescaler). Refer to Fig. 6, CLK=Fosc/2 or CLK=Fosc/4 is depended on the CODE option bit CLKS. CLK=Fosc/2 if CLKS bit is "0", and CLK=Fosc/4 if CLKS bit is "1". If TCC signal source is from external clock input, TCC will increase by 1 on every falling edge or rising edge of TCC pin. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even the oscillator driver has been turned off (i.e. in sleep mode). During the normal operation or the sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the normal mode by software programming. Refer to WDTE bit of IOC0E register. With no presacler, the WDT time-out period is approximately 18 ms.
*
*
* This specification is subject to be changed without notice.
B3-10
12.29.1999
EM78P447S
VI.4 I/O Ports The I/O registers, Port 5, Port 6 and Port 7, are bi-directional tri-state I/O ports. The function of Pull-high, R-option and Open-drain can be enabled internally by CONT and IOCE respectively. There is an input status changed interrupt (or wake-up) function on Port 6, P74 and P75. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6 and Port 7 are shown in Fig. 7 (a) & (b) respectively.
CLK(=Fosc/2 or Fosc/4) Data Bus
0 TCC Pin 1
M U X
1 0
M U X
SYNC 2 cycles
TCC(R1)
TE
TS
PAB
TCC overflow interrupt
0 WDT 1
M U X
8-bit Counter
PSR0~PSR2 PAB WTE (in IOCE) 8-to-1 MUX 0 1 MUX PAB
WDT time-out
Fig. 6
Block diagram of TCC and WDT
PCRD
QPD R CLK C QL
PCWR
PORT
QPD R CLK C QL
IOD PDWR PDRD
0 1
M U X
Fig. 7(a) The circuit of I/O port and I/O control register
* This specification is subject to be changed without notice.
B3-11
12.29.1999
EM78P447S
PCRD VCC ROC
Weekly Pull-up
QPD R CLK C QL
PCWR
PORT
QPD R CLK QC L
IOD PDWR PDRD
0 Rex* 1
M U X
* The Rex is 560K ohm external resistor Fig. 7(b) The circuit of I/O port with R-option (P70,P71)
VDD D CLK
Q CLR
Oscillator
CLK
Power-on Reset
WTE WDT Timeout
WDT
18 ms
Reset
RESET
Fig. 8 Block diagram of Reset of controller VI.5 RESET and Wake-up 1. RESET The RESET can be caused by (1) Power-on reset, (2) /RESET pin input "low", or (3) WDT timeout. (if enabled)
* This specification is subject to be changed without notice.
B3-12
12.29.1999
EM78P447S
Note that only power-on reset, or only voltage detector in Case (1) is enabled in the system by CODE option bit. Refer to Fig. 8. The device will be kept in a RESET condition for a period of approx. 18ms (one-oscillator startup timer period) after the reset is detected. Once the RESET occurs, the following functions are performed. * The oscillator is running, or will be started. * The Program Counter (R2) is set to all "1". * All I/O port pins are configured as input mode (high-impedance state). * The Watchdog Timer and prescaler are cleared. * Upon power-on, the bits 5~6 of R3 are cleared. * Upon power-on, the upper 2 bits of R4 are cleared. * The bits of the CONT register are set to all "1" except the bit 6 (INT flag). * IOCB register is set to all "1" (disable P60~P67 wake-up function). * Bits 3 and 6 of the IOCE register are cleared, and Bits 0,4 and 5 are set to "1". * Bits 0 and 3 of R3F register and bits 0 and 3 of IOCF register are cleared. Executing the "SLEP" instruction (named as SLEEP1 mode) can perform the sleep mode. While entering sleep mode, WDT (if enabled) is cleared but keeps running. The controller can be awakened by (1) (2) External reset input on /RESET pin; WDT time-out (if enabled).
The two cases will cause the controller EM78P447S to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). In addition to the basic SLEEP1 MODE, EM78P447S has another sleep mode (caused by clearing "SLPC" bit of IOCE register, named as SLEEP2 MODE). In the SLEEP2 MODE, the controller can be awakened by (a). Any one of wake-up pins is "0". Please refer to Fig. 5. When waking, the controller will continue to execute the successive address. In this case, before entering SLEEP2 MODE, the wake-up function of the trigger sources (P60~P67, and P74~P75) should be selected (e.g. input pin) and enabled (e.g. pull-high, wakeup control). One caution should be noticed is that after waking up, the WDT is enabled if Code Option bit WTC is "1". The WDT operation (to be enabled or disabled) should be appropriately controlled by software after waking up. WDT time-out (if enabled) or external reset input on /RESET pin will cause the controller to reset.
(b).
Table 3 The summary of the initialized values for registers Address Name Reset Type Bit 7 N/A IOC5 Bit Name C57 TYPE AB Power-on 01 /RESET and WDT 01 Wake-up from Pin Changed 0 P N/A IOC6 Bit Name C67 Power-on 1 /RESET and WDT 1 Wake-up from Pin Changed P N/A IOC7 Bit Name C77 Power-on 1
B3-13
Bit 6 Bit 5 Bit 4 Bit 3 C56 C55 C54 C53 ABABAB 010101 1 010101 1 0P0P0P P C66 C65 C64 C63 1 1 1 1 1 1 1 1 P P P P C76 C75 C74 C73 1 1 1 1
12.29.1999
Bit 2 Bit 1 Bit 0 C52 C51 C50 1 1 1 1 1 1 P P P C62 C61 C60 1 1 1 1 1 1 P P P C72 C71 C70 1 1 1
* This specification is subject to be changed without notice.
EM78P447S
Address Name Reset Type /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit 7 1 P /PHEN 1 1 P U P P 0 0 P 1 1 **0/P GP 0 0 P RSR1 0 0 P P57 U P P P67 U P P P77 U P P X U U U 1 1 P X U U U Bit 6 1 P /INT 0 P P U P P 0 0 P 1 1 **0/P PS1 0 0 P RSR0 0 0 P P56 U P P P66 U P P P76 U P P X U U U 1 1 P ODE 0 0 P Bit 5 1 P TS 1 1 P U P P 0 0 P 1 1 **0/P PS0 0 0 P U P P P55 U P P P65 U P P P75 U P P X U U U 1 1 P WTE 1 1 1 Bit 4 1 P TE 1 1 P U P P 0 0 P 1 1 **0/P T 1 t t U P P P54 U P P P64 U P P P74 U P P X U U U 1 1 P SLPC 1 1 1 Bit 3 1 P PAB 1 1 P U P P 0 0 P 1 1 **0/P P 1 t t U P P P53 U P P P63 U P P P73 U P P EXIF 0 0 P 1 1 P ROC 0 0 P Bit 2 Bit 1 1 1 P P PSR2 PSR1 1 1 1 1 P P U U P P P P 0 0 0 0 P P 1 1 1 1 **0/P **0/P Z DC U U P P P P U U P P P P P52 P51 U U P P P P P62 P61 U U P P P P P72 P71 U U P P P P X X U U U U U U 1 1 1 1 P P X X U U U U U U Bit 0 1 P PSR0 1 1 P U P P 0 0 P 1 1 **0/P C U P P U P P P50 U P P P60 U P P P70 U P P TCIF 0 0 P 1 1 P /WUE 1 1 P
N/A
CONT
0X00
R0(IAR)
0X01
R1(TCC)
0X02
R2(PC)
0X03
R3(SR)
0x04
R4(RSR)
0x05
R5(P5)
0x06
R6(P6)
0x07
R7(P7)
0x3F
R3F(ISR)
0x0B
IOCB
0x0E
IOCE
* This specification is subject to be changed without notice.
B3-14
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EM78P447S
Address 0x0F Name IOCF Reset Type Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit Name Power-on /RESET and WDT Wake-up from Pin Changed Bit 7 X U U U U P P Bit 6 X U U U U P P Bit 5 X U U U U P P Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X EXIE X X TCIE U 0 U U 0 U 0 U U 0 U P U U P U U U U U P P P P P P P P P P
0x08 ~ 0x3E
R8~R3E
** To execute next instruction after the "SLPC" bit status of IOCE register being on high-to-low transition. X: not used. U: unknown or don't care. P: previous value before reset. t: check Table 4. 2. The status of T and P of STATUS register A RESET condition can be caused by the following events: (1) A power-on condition, (2) A high-low-high pulse on /RESET pin, and (3) Watchdog Timer time-out. The values of T and P, listed in Table 4 can be used to check how the processor wakes up. Table 5 shows the events which may affect the status of T and P.
Table 4 The values of T and P after RESET Reset Type Power-on /RESET during operating mode /RESET wake-up during SLEEP1 mode /RESET wake-up during SLEEP2 mode WDT during operating mode WDT wake-up during SLEEP1 mode WDT wake-up during SLEEP2 mode Wake-up on pin changed during SLEEP2 mode * P: Previous status before reset
T 1 *P 1 *P 0 0 0 *P
P 1 *P 0 *P *P 0 *P *P
Table 5 The status of T and P being affected by events Event Power-on WDTC instruction WDT time-out SLEP instruction Wake-up on pin changed during SLEEP2 mode * P: Previous value before reset T 1 1 0 1 *P P 1 1 *P 0 *P
* This specification is subject to be changed without notice.
B3-15
12.29.1999
EM78P447S
VI.6 Interrupt The EM78P447S has two interrupts listed below: (1) TCC overflow interrupt. (2) External interrupt (/INT) . R3F, the interrupt status register, records the interrupt requests in the relative flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (when enabled) occurs, the next instruction will be fetched from address 001H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in R3F. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of R3F and IOCF. Refer to Fig. 9. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). When an interrupt is generated by the INT instruction (when enabled), the next instruction will be fetched from address 002H.
VCC
D /IRQn
P R CLK C L
Q
IRQn . . IRQm
/INT
Q
RFRD ENI/DISI
R3F
Q
P R C L
D CLK
IOD IOCFWR
Q /RESET IOCF
IOCFRD
RFWR
Fig. 9 Interrupt input circuit VI.7 Oscillator 1 . Oscillator Modes The EM78P447S can be operated in three different oscillator modes. There are External RC oscillator mode (ERC), High XTAL oscillator mode (HXT) and Low XTAL oscillator mode(LXT). Users can select one of them by programming MS, HLF, and HLP in the CODE Option Register. Table 6 depicts how these three modes to be defined.
* This specification is subject to be changed without notice.
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EM78P447S
The up-most limited operation frequency of crystal/resonator on the different VDDs is listed in Table 7. Table 6 Oscillator Modes defined by MS, HLF, HLP Mode External RC oscillator mode High XTAL oscillator mode Low XTAL oscillator mode MS 0 1 1 HLF *X 1 0 HLP *X *X 0
1. X, Do not care 2. The transient point of system frequency between HXT and LXY is around 400 KHz. Table 7 The summary of maximum operating speeds Conditions VDD (V) 2.5 3 Two clocks 5 6.4 2.5 3 Four clocks 5 6.5
Fxt max. (MHz) 8 12 20 21 16 24 40 42
2.
Crystal Oscillator/Ceramic Resonators(XTAL) EM78P447S can be driven by an external clock signal through the OSCI pin as shown in Fig. 10. In the most applications, pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 11 depicts the circuit. It is the same no matter in the HXT mode or in the LXT mode. Table 8 recommends the values of C1 and C2. Since each resonator has its own attribute, users should refer to their specifications for appropriate values of C1 and C2. RS, a serial resistor may be necessary for AT strip cut crystal or low frequency mode.
OSCI OSCO EM78P447S Ext. Clock
Fig. 10 Circuit for External Clock Input Table 8 Capacitor Selection Guide for Crystal Oscillator Ceramic Resonators Oscillator Type Frequency Mode Frequency C1 (pF) 455 KHz 100~150 1.00 MHz 40~80 Ceramic Resonator HXT 2.0 MHz 20~40 4.0 MHz 10~30
C2 (pF) 100~150 40~80 20~40 10~30
* This specification is subject to be changed without notice.
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EM78P447S
Oscillator Type Frequency Mode LXT Crystal Oscillator HXT Frequency 32.768 KHz 100 KHz 200 KHz 455 KHz 1.0 MHz 2.0 MHz 4.0 MHz
C1 OSCI EM78P447S OSCO RS C2
C1 (pF) 25 25 25 20~40 15~30 15 15
C2 (pF) 15 25 25 20~150 15~30 15 15
XTAL
Fig. 11 Circuit for Crystal/Resonator
330 330
OSCI 7404 7404 C 7404
EM78P447S
XTAL
Fig. 12 Circuit for Crystal/Resonator (Series Mode)
4.7K 10K VDD 7404 OSCI
EM78P447S
7404 10K XTAL C1 C2
Fig. 13 Circuit for Crystal/Resonator (Parallel Mode) 3. RC Oscillator Mode For some applications whose timing need not be calculated precisely, the RC oscillator (Fig. 14) offers a lot of cost savings. Nevertheless, it should be aware that the frequency of the RC oscillator is the function of the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even the operation temperature. Moreover to this, the
* This specification is subject to be changed without notice.
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EM78P447S
frequency also changes slightly from one chip to another due to the process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, as well as the value of Rext should not be greater than 1M ohm. If they can not be kept in this range, the frequency is affected easily by noise, humidity and leakage. The smaller Rext the RC oscillator has, the faster frequency it gets. On the contrary, for very low Rext values, for instance, 1K, the oscillator becomes unstable because the NMOS can not discharge the current of the capacitance correctly. On a basis of the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types and the ways of PCB layout will effect the system frequency.
VCC Rext
OSCI
EM78P447S
Cext
Fig. 14 Circuit for External RC Oscillator Mode
Table 9 RC Oscillator Frequencies Cext 20pF Rext 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k Average Fosc @ 5V, 25C 4.32 MHz 2.83 MHz 1.62 MHz 184 KHz 1.39 MHz 950 KHz 500 KHz 54 KHz 580 KHz 390 KHz 200 KHz 21 KHz Average Fosc @ 3V, 25C 3.56 MHz 2.8 MHz 1.57 MHz 187 KHz 1.35 KHz 930 KHz 490 KHz 55 KHz 550 KHz 380 KHz 200 KHz 21 KHz
100pF
300pF
* 1. Measured on DIP packages. 2. Design reference only
* This specification is subject to be changed without notice.
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EM78P447S
VI.8 CODE Option Register The EM78P447S has one CODE option word which is not a part of the normal program memory. The option bits can not be accessed during normal program execution. 12 MS * 11 ENWDTB 10 CLKS 9 /PT 8 HLF 7 HLP 6 TYP 5~0 ------
*
*
*
*
*
*
*
*
Bit 12 (MS): Oscillator type selection. 0: RC type 1: XTAL type Bit 11 (/ENWTDB): Watchdog Timer enable bit. 0: Enable 1: Disable Bit 10 (CLKS): Instruction period option bit. 0: two oscillator periods 1: four oscillator periods Refer to the section of Instruction Set. Bit 9(/PT): Protect Bit. 0: Protect Enable 1: Protect Disable Bit 8(HLF): XTAL frequency selection. 0: XTAL2 type (Low frequency, 32.768KHz) 1: XTAL1 type (High frequency) This bit is useful only when Bit 0 (MS) is "1". When MS is "0", HLF must be "0". Bit 7(HLP): Power consumption selection. 0: Low power 1: High power Bit 6(Type): Type selection for EM78P447SA or B. 0: EM78P447SB 1: EM78P447SA Bit 5 and Bit 4 : Reserved. The bit5 set to"1" all the time The bit4 set to "0" all the time Bit 3~0: User's ID code.
VI.9 Power-on Considerations Any microcontroller is not warranted to start proper operation before the power supply stays in its steady state. EM78P447S is equipped with Power On Voltage Detector (POVD) which detective level is 2.0V. The circuitry eliminates the extra external reset circuit. It will work well if Vdd rises quickly enough (10 ms or less). In many critical applications, however, extra devices are still required to assist in solving power-up problems. VI.10 External Power-on Reset Circuit The circuit shown in Fig. 15 implements an external RC to produce the reset pulse. The pulse width (time constant) should keep long enough until Vdd has reached minimum operation voltage. This circuit is used when the power
* This specification is subject to be changed without notice.
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12.29.1999
EM78P447S
supply has slow rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be greater than 40K. In this way, the voltage in pin /RESET will be held below 0.2V. The diode (D) acts a short circuit at the moment of power-down. The capacitor, C, will be discharged rapidly and fully. Rl, the currentlimited resistor, protects against a high discharging current or ESD (electrostatic discharge) flowing to pin /RESET.
VDD /RESET R D
EM78P447S
Rin C
Fig. 15 VI.11 Residue Voltage Protection
External Power-up Reset Circuit
In some applications, replacing battery as an instance, device power (Vdd) is taken off and recovered within a few seconds. A residue voltage which trips below Vdd min but not to zero may exist. This condition may cause a poor power-on reset. Fig. 16 and Fig. 17 show how to build the residue voltage protection circuit
VDD VDD Q1 10K 33K
EM78P447S
/RESET
100K IN4684
Fig. 16 Circuit 1 for the residue voltage protection
VDD
VDD Q1 R1
EM78P447S
/RESET
R3
R2
Fig. 17 Circuit 2 for the residue voltage protection
* This specification is subject to be changed without notice.
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EM78P447S
VI.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ......). In this case, the execution takes two instruction cycles. Under some conditions, if the specification of the instruction cycle is not suitable for some applications, they can be modified as follows: (A) One instruction cycle consists of 4 oscillator periods. (B) "JMP", "CALL", "RET", "RETL", "RETI", and the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") tested to be true are executed within two instruction cycles. The instructions that write to the program counter also take two instruction cycles. The Case (A) is selected by the CODE option bit, called CLKS. One instruction cycle consists of two oscillator clocks if CLKS is low, and consists of four oscillator clocks if CLKS is high. Note that once 4 oscillator periods within one instruction cycle is selected in Case (A), the internal clock source to TCC is CLK=Fosc/4 instead of Fosc/ 2 that is shown in Fig. 6. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O registers can be operated as general registers. That is, the same instruction can operate on I/O register. The symbol "R" represents a register designator which specifies which one of the registers (including operational registers and general purpose registers) to be utilized by the instruction. The symbol "b" represents a bit field designator which selects the number of the bit located in the register "R" affected by the operation. The symbol "k" represents an 8 or 10-bit constant or literal value.
* This specification is subject to be changed without notice.
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EM78P447S
Table 10 The list of the instruction set of EM78P447S INSTRUCTION BINARY 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0 0 0 0000 0000 0000 0000 0001 0001 0001 0001 0000 0001 0010 0011 HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R OPERATION No Operation Decimal Adjust A ACONT 0WDT, Stop oscillator 0WDT AIOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONTA IOCRA R2+AR2 Bits 8~9 of R2 unchanged AR 0A 0R R-AA R-AR R-1A R-1R AvVRA AvVRR A & RA A & RR A RA A RR A + RA A + RR RA RR /RA /RR R+1A R+1R R-1A, skip if zero R-1R, skip if zero R(n)A(n-1) R(0)C, CA(7) R(n)R(n-1) R(0)C, CR(7) R(n)A(n+1) R(7)C, CA(0) R(n)R(n+1) R(7)C, CR(0)
12.29.1999
STATUS AFFECTED None C None T,P T,P None None None None None None None Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C
0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0110 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr
* This specification is subject to be changed without notice.
B3-23
EM78P447S
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
INSTRUCTION BINARY 0111 01rr rrrr 0111 10rr rrrr 0111 11rr rrrr 100b bbrr rrrr 101b bbrr rrrr 110b bbrr rrrr 111b bbrr rrrr 00kk kkkk kkkk 01kk kkkk kkkk 1000 kkkk kkkk 1001 kkkk kkkk 1010 kkkk kkkk 1011 kkkk kkkk 1100 kkkk kkkk 1101 kkkk kkkk 1110 0000 0001 1111 kkkk kkkk
HEX 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1Fkk
MNEMONIC SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k
OPERATION R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1[SP], (Page, k) PC (Page, k) PC k ANone AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP], 001H PC k+A A
STATUS AFFECTED None None None None None None None None None Z Z Z None Z,C,DC None Z,C,DC
This instruction can operate on IOC5~IOC7, IOCB, IOCE, IOCF only. This instruction is not recommended to operate on RF. This instruction cannot operate on RF.
* This specification is subject to be changed without notice.
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EM78P447S
VII. ABSOLUTE MAXIMUM RATINGS
Items Temperature under bias Storage temperature Input voltage Output voltage Sym. TOPR TSTR VIN VO Condition Rating 0C to 70C -65C to 150C -0.3V to +6.0V -0.3V to +6.0V
VIII. DC ELECTRICAL CHARACTERISTIC (Ta=0C ~ 70C, VDD=5.0V, VSS=0V)
Parameter XTAL: VDD to 3V XTAL: VDD to 5V RC : VDD to 5V Input Leakage Current for input pins Input High Voltage Input Low Voltage Input High Threshold Voltage Input Low Threshold Voltage Clock Input High Voltage Clock Input Low Voltage Output High Voltage (Port 5,6,7) Output Low Voltage (Port 5,6) Output Low Voltage (Port7) Pull-high current Power-down current Power-down current Operating supply current (VDD=5V) at two cycles/two clocks Operating supply current (VDD=5V) at two cycles/two clocks Operating supply current (VDD=3V) at two cycles/two clocks Operating supply current (VDD=3V) at two cycles/two clocks Sym. Fxt FRC IIL VIH VIL VIHT VILT VIHX VILX VOH1 VOL1 VOL2 IPH ISB1 ISB2 ICC1 Condition Two clocks R : 5.1K , C : 100pF VIN = VDD, VSS Ports 5, 6 Ports 5, 6 /RESET, TCC,INT /RESET, TCC,INT OSCI OSCI IOH = -10.0mA IOL = 9.0mA IOL = 14.0mA Pull-high active, input pin at VSS All input and I/O pins at VDD, output pin floating, WDT enabled All input and I/O pins at VDD, output pin floating, WDT disabled /RESET='High', Fosc=4MHz (HLF="1", CK2="0"), output pin floating, WDT disabled /RESET='High', Fosc=10MHz (HLF="1",CK2="0"),output pin floating, WDT disabled /RESET='High', Fosc=32.768KHz (HLF="0",CK2="0"), output pin floating, WDT disabled /RESET='High', Fosc=32.768KHz (HLF="0",CK2="0"), output pin floating, WDT enabled -50 -100 Min. DC DC F20% Typ. Max. 4.0 20.0 F20% 1 Unit MHz MHz KHz A V V V V V V V V V A A A
950
2.0 0.8 2.0 0.8 3.5 1.5 2.4 0.4 0.4 -240 7 1
2.2
mA
ICC2
5
mA
ICC3
15
25
30
A
ICC4
-
30
35
A
* This specification is subject to be changed without notice.
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EM78P447S
IX. VOLTAGE DETECTOR ELECTRICAL CHARACTERISTIC (Ta = 25C)
Parameter Detect voltage Release voltage Current consumption Operating voltage Temperature characteristic of Vdet VDD reset voltage Symbol Vdet Vrel Iss Vop Vdet/ Ta Vreset Condition Min. 1.9 VDD = 5V 0.7* 0C Ta 70C Ta=25C Typ. 2.0 Vdet x1.05 Max. 2.1 5 5.5 -2 1.9 Unit V V A V mV/C V
* When the voltage of VDD rises between Vop=0.7V and Vdet, the output of voltage detector must be "Low".
X.
AC ELECTRICAL CHARACTERISTICS (Ta=0C ~ 70C, VDD=5.0V5%, VSS=0V)
Parameter Symbol Dclk Tins Ttcc Tdrh Twdt Tset Thold Tdelay XTAL Type RC Type Ta = 25C Ta = 25C Condition Min. 45 100 500 (Tins+20)/N* 16.2 16.2 0 20 50 Typ. 50 Max. 55 DC DC Unit % ns ns ns ms ms ns ns ns
Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time Watchdog Timer period Input pin setup time Input pin hold time Output pin delay time
Cload=20pF
Note : N* = selected prescaler ratio.
* This specification is subject to be changed without notice.
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EM78P447S
XI. TIMING DIAGRAMS
AC Test Input/Output Waveform
2.4 2.0 0.8 0.45 TEST PONITS 0.8 2.0
AC Testing : Input is driven at 2.4V for logic "1", and 0.45V for logic "0". Timing measurements are made at 2.0V for logic "1", and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLK="0")
Tins
CLK
TCC
Ttcc
* This specification is subject to be changed without notice.
B3-27
12.29.1999

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